Work Experience

Cadence Design Systems, Inc

Software Engineer • Oct, 2017 — Mar, 2019

Cadence is one of the '2019 Fortune 100 Best Companies to Work For'

  • Focused on layout editing tool SiP (C/C++) and system planning tool OrbitIO (JAVA)
  • Worked closely with software architects in North America to develop new features
  • Supported Taiwan Semiconductor (TSMC) to develop certificated reference flow
  • Enhanced metal-filling/degassing functions in SiP with 40x/10x speedups

Skills

Version Control Systems

Git, GitHub, Perforce

Programing Languages

C/C++, Python, Java, Go, Matlab

Python Packages

Scikit-Learn, PyTorch, NumPy, Matplotlib, SciPy, TensorBoard, Pandas, JupyterLab

Miscellaneous

Docker, MySQL, AWS, OpenMP, OpenCV, CUDA, Boost C++, CMake

EDA Tools

Cadence SiP, Cadence OribitIO, Cadence Virtuoso, Synopsys Design Compiler, Synopsys IC Compiler, KiCad, Autodesk EAGLE

Languages

English (Fluent), Mandarin Chinese (Native)

Education

University of California, San Diego

Doctor of Philosophy • 2019 — Present

  • Major - Computer Science and Engineering (Overall GPA 4.00/4.00)
  • Advisor - Prof. Chung-Kuan Cheng

National Taiwan University

Master of Science • 2015 — 2017

  • Major - Electronics Engineering (Overall GPA 4.23/4.30)
  • Advisor - Prof. Yao-Wen Chang

Koç University

Undergraduate Exchange Student • 2015

National Chiao Tung University

Bachelor of Science • 2011 — 2015

  • Major - Electronics Engineering (Overall GPA 4.02/4.30)
  • Minor - Computer Science

Research Experiences

Research Assistant • May, 2019 — Present

  • 24-hour, No-Human-In-The-Loop layout design for SOC, Package and PCB
  • Machine-learning-driven parallel search and optimization
  • Focused on a multi-objective cost-driven path finding problem with complex constraints
  • Main developer of the open source PCB Router

Research Assistant • Sep, 2016 — Aug, 2017

  • Focused on RDL routing for TSMC InFO_PoP advanced packaging technologies
  • Proposed to transform a routing sequence into two directed acyclic graphs to minimize multiple objectives
  • Experimental results showed that our router can achieve 100% routablility for all given test cases

Selected Projects

Winter, 2020

Fall, 2019

  • Dataset is available at UCI Machine Learning Repository
  • Mixed uni- & bi-gram words with TF-IDF as features to represent drug review text
  • Adopted random forest regressor to achieve R^2 with 0.79 when predicting drug rating

Publication

T.-C. Lin, D. Merrill and Y.-Y. Wu, C. Holtz, and C.-K. Cheng “A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pairs,” in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), January 2021 (to appear)

T.-C. Lin, C.-C. Chi, and Y.-W. Chang, “Redistribution Layer Routing for Wafer-Level Integrated Fan-Out Package-on-Packages,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2017 (acceptance rate: 105/399=26%)

B.-Q. Lin, T.-C. Lin, and Y.-W. Chang, “Redistribution Layer Routing for Integrated Fan-Out Wafer-Level Chip-Scale Package,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2016 (acceptance rate: 97/409=24%)

Recognition

J. Yang Scholarship Award

Institute of Engineering in Medicine, UCSD • 2020

Academic Scholarship Award

Graduate Institute of Electronics Engineering, NTU • 2016, 2017

Patent

B.-Q. Lin, T.-C. Lin, C.-Y. Yang, and Y.-W. Chang, “Redistribution Layer Routing for Integrated Fan-Out Wafer-Level Chip-Scale Packages,” US Patent US 2018/0032660 A1, Feb. 2018